Faster Software Packet Processing on FPGA NICs with eBPF Program WarpingMobile World Capital Barcelona
FPGA NICs can improve packet processing performance, however, programming them is difficult, and existing solutions to enable software packet processing on FPGA either provide limited packet processing speed, or require changes to programs and to their development/deployment life cycle.
We address the issue with program warping, a new technique that improves throughput replacing several instructions of a packet processing program with an equivalent runtime programmable hardware implementation. Program warping performs static analysis of a packet processing program, described with Linux’s eBPF, to identify subsets of the program that can be implemented by an optimized FPGA pipeline, the warp engine. Packets handled by the warp engine are eventually delivered to a regular eBPF program executor, along with their program context (registers, stack), to complete execution of those program parts that cannot be efficiently pipelined.
We prototype program warping on a 100Gbps FPGA NIC, extending hXDP, a state-of-the-art eBPF processor for FPGA, and measure its performance running 6 unmodified real-world eBPF programs, including deployed applications such as Katran and Suricata. Our prototype runs at 250MHz, uses less than 15% of the FPGA resources, and improves hXDP throughput by 1.2-3x in most cases, and up to 18x.
- Marco Bonola, Axbryd/CNIT.
- Giacomo Belocchi, Axbryd/University of Rome Tor Vergata.
- Angelo Tulumello, Axbryd/University of Rome Tor Vergata.
- Marco Spaziani Brunella, Axbryd/University of Rome Tor Vergata.
- Giuseppe Siracusano, NEC Laboratories Europe.
- Giuseppe Bianchi, University of Rome Tor Vergata.
- Roberto Bifulco, NEC Laboratories Europe.
You can also read this scientific paper in Zenodo.